1. Field of the Invention
The present invention relates to a clock supply circuit in a receiving LSI of digital broadcasting for supplying a clock signal, for example, to a processing circuit such as a receiving circuit and a DSP, more particularly relates to a clock supply circuit for supplying a clock signal whose frequency is switched in accordance with an amount out-of-sync to maintain synchronization with transmission signals, also for supplying a clock signal whose frequency is controlled in accordance with a processing load of the processing circuit, etc.
2. Description of the Related Art
A receiver of digital audio broadcasting (DAB) receives a broadcast signal having a certain cycle transmitted from a broadcast station and demodulates and decodes the signal in accordance with the received signal to reproduce an audio signal. Therefore, it is necessary to maintain synchronization of the local clock signal supplied to the receive circuit with respect to the broadcast signal to retrieve the broadcast signal correctly. That is, to provide a clock signal of a certain frequency same as that of the broadcast signal, for example, 24 MHZ, to the receive circuit. Therefore, in a conventional receiver, for example, a voltage-controlled oscillator is used for generating the local clock signal in a clock generating circuit wherein the synchronization of the local clock signal with the broadcast signal is maintained by detecting an amount of offset with respect to the broadcast signal (amount out-of-sync) on a time axis, and controlling the oscillating frequency of the oscillator.
Also, it is desirable that a clock signal of a variable frequency controlled in frequency in accordance with a processing load is supplied to a processing circuit for processing the received signal, for example, a processing circuit which includes a DSP circuit and expands an MPEG stream. This is because the processing ability of the DSP is determined in accordance with the frequency of the supplied clock signal. The higher the clock frequency, the higher the processing ability of the DSP, and the more information which can be processed per unit time.
In the case of digital audio broadcasting, the broadcast signal differs in accordance with the broadcast signal standard. For example, the number of data points differs in each symbol in an OFDM modulated signal in accordance with a broadcast mode. Therefore, on the receiving side, the processing load of an MPEG decoding circuit for expanding an MPEG stream demodulated according to the OFDM scheme changes in accordance with the broadcast mode.
In the past, as a means to solve this problem, in a receiving circuit, a plurality of DSPs were arranged and the processing load was distributed among a plurality of processing circuits so as to reduce loads of each processing circuit.
In the above conventional method, however, a plurality of the same blocks are provided, so the circuit size is increased, which leads to an increase of electric power consumption and waste.
Thus, as another means of solution, an external oscillator is made to generate a high frequency clock and that high frequency clock signal is divided inside the LSI so as to supply a high frequency clock signal of a variable frequency to the DPS and other processing blocks in addition to a reference clock signal of a constant frequency. However, when the frequency of the external clock signal becomes higher, the power consumption becomes larger by that amount. Therefore, in the past, this was dealt with stopping the supply of the clock signal to the DSP after the end of processing of the DSP, that is, by a so-called sleep mode. As a result, there is the disadvantage that control becomes complicated due to switching of the operation mode of the DSP and sufficient effects cannot be obtained.
Also, in the receive circuit, a method for generating a local clock signal was taken which maintained synchronization with the broadcast signal by using a voltage-controlled oscillator and controlling the oscillation frequency in accordance with the amount of the offset on the time axis. Since the voltage-controlled oscillator used was an expensive one such as a VCXO (voltage-controlled crystal oscillator), it led to an increase of the cost. Further, since feedback control was performed to generate a control signal in accordance with the offset and output the same to the VCXO, there was a disadvantage that the circuit configuration became complicated and the circuit scale became large.